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A 14-b 2.5 MSPS pipelined ADC with on-chip EPROM

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1 Author(s)
Mercer, D.A. ; Analog Devices Inc., Wilmington, MA, USA

A 14-b 2.5 MSPS, multistage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, “write once” EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as ±1.5 LSB and differential nonlinearity errors of ±0.5 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5 V reference and is built on a 2 μm 10 V BiCMOS process and consumes 500 mW of power

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 1 )

Date of Publication:

Jan 1996

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