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Pipelined adders

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2 Author(s)
Dadda, L. ; Dept. of Electron. & Inf., Politecnico di Milano, Italy ; Piuri, V.

A well-known scheme for obtaining high throughput adders is a pipeline in which each stage contains an array of half-adders performing a carry-save addition. This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder. Such schemes offer a considerable savings of components while preserving high throughput. These schemes can be generalized by using (p,q) parallel counters to obtain pipelined adders for more than two numbers

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Computers, IEEE Transactions on  (Volume:45 ,  Issue: 3 )