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Aliasing error for a mask ROM built-in self-test

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2 Author(s)
K. Iwasaki ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; S. Nakamura

To develop better ROM BIST techniques we first experimentally surveyed cell faults, word-line faults, bit-line faults, delay faults and other types of faults occurring in 1,000 faulty mask ROM chips. We found that most of the stuck-at faults were within a single mat. We then theoretically analyzed the aliasing probability for a mask ROM containing a fault or faults within a single mat. To experimentally evaluate BIST aliasing errors we implemented six MISRs on a custom board and observed actual aliasing errors. The experimentally measured aliasing probabilities agreed with the probabilities derived theoretically. No aliasing error occurred for the 16-stage, 8-input MISR

Published in:

IEEE Transactions on Computers  (Volume:45 ,  Issue: 3 )