Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Generation of tenacious tests for small gate delay faults in combinational circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Takahashi, H. ; Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan ; Watanabe, T. ; Takamatsu, Y.

In this paper, we present a test for small gate delay faults in combinational circuits, called a tenacious test and describe a method for generating tenacious tests. We consider a single gate delay fault in a circuit on the assumption of that each gate has some appropriate gate delay. First, we introduce a tenacious test ⟨V1, V2⟩ for a small gate delay fault on line L. The tenacious test ⟨V1, V2⟩ can propagate the effect of a small gate delay fault at line L to primary outputs by the delay effect. Next, we present a method for generating tenacious tests by using a timed seven-valued calculus with consideration of delay of each gate in a circuit under test. Finally, experimental results are demonstrated for gate delay faults on ISCAS'85 benchmark circuits. Experimental results show that we can obtain tenacious tests for small gate delay faults with high fault coverage

Published in:

Test Symposium, 1995., Proceedings of the Fourth Asian

Date of Conference:

23-24 Nov 1995