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Generation of tenacious tests for small gate delay faults in combinational circuits

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3 Author(s)
Takahashi, H. ; Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan ; Watanabe, T. ; Takamatsu, Y.

In this paper, we present a test for small gate delay faults in combinational circuits, called a tenacious test and describe a method for generating tenacious tests. We consider a single gate delay fault in a circuit on the assumption of that each gate has some appropriate gate delay. First, we introduce a tenacious test ⟨V1, V2⟩ for a small gate delay fault on line L. The tenacious test ⟨V1, V2⟩ can propagate the effect of a small gate delay fault at line L to primary outputs by the delay effect. Next, we present a method for generating tenacious tests by using a timed seven-valued calculus with consideration of delay of each gate in a circuit under test. Finally, experimental results are demonstrated for gate delay faults on ISCAS'85 benchmark circuits. Experimental results show that we can obtain tenacious tests for small gate delay faults with high fault coverage

Published in:

Test Symposium, 1995., Proceedings of the Fourth Asian

Date of Conference:

23-24 Nov 1995