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A parallel sequential test generation system DESCARTES based on real-valued logic simulation

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3 Author(s)
Date, H. ; Res. Lab., Hitachi Ltd., Ibaraki, Japan ; Nakao, M. ; Hatayama, K.

This paper presents a parallel, automatic test generation system, DESCARTES, for synchronous sequential circuits. This system parallelizes the test generation algorithm based on real-valued logic simulation. By addition of a redundant fault identification program and an algorithmic test generation program, test generation is speeded up and test quality is improved. Experimental results for ISCAS '89 benchmark sequential circuits illustrate the efficiency of this approach

Published in:

Test Symposium, 1995., Proceedings of the Fourth Asian

Date of Conference:

23-24 Nov 1995