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pASIC 2 FPGA family: the ultimate Verilog/VHDL silicon solution

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1 Author(s)

QuickLogic's new pASIC 2 FPGAs resolve the utilization/performance dilemma for HDL users. pASIC 2 is a family of seven devices ranging from 3000 to 20,000 usable gates and 84 to 352 package pins. A new 0.65μ three-layer metal process moves QuickLogic's metal-layer amorphous silicon ViaLink antifuse technology above the transistor silicon which allows abundant high speed interconnect and routing resources with relatively small die sizes. The benefits to the user are a low-cost family with high gate densities and 100% routability and pin-out maintainability

Published in:

WESCON/'95. Conference record. 'Microelectronics Communications Technology Producing Quality Products Mobile and Portable Power Emerging Technologies'

Date of Conference:

7-9 Nov. 1995