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Ground bounce study of 304 lead interposer MQFP with on-chip decoupling capacitor test die

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3 Author(s)
Huang, C.C. ; VLSI Technol. Inc., San Jose, CA, USA ; Loh, B. ; Wong, F.

As clock frequency and the number of I/O's increase in ASIC devices, the ground bounce problems of packages begin to seriously impact system performance. To resolve these problems, high performance packages must be used in system design. This, however, can add significantly to the cost of the system. One of the methods to optimize the cost, manufacturability and the performance of packages is to add decoupling capacitors to the power and the ground of the die or packages. However, adding decoupling capacitors always increases the inductance effects. A systematic approach is needed to determine the correct method of using the decoupling capacitor technique with minimal inductive effects. This paper presents the ground bounce data of 304 1d Interposer MQFP (multilayer quad flat packaging) with on-chip decoupling capacitor test die and 208 1d Single-Layer PPGA (plastic pin grid array) with off-chip decoupling capacitor versus various simultaneous switching output (SSO) numbers and loadings. This paper shows that both on-chip and off-chip methods help in reducing the ground bounce. This paper also shows that on-chip decoupling capacitor test die increases the overall operation frequency of the system as compared to the test die without the decoupling capacitors. General concepts, the cost and the manufacturability of the off-chip capacitor and the test die with and without on-chip capacitors is discussed

Published in:

Northcon 95. I EEE Technical Applications Conference and Workshops Northcon95

Date of Conference:

10-12 Oct 1995