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Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories

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3 Author(s)
Li-Ming Denq ; Nat. Tsing Hua Univ. ; Yu-Tsao Hsing ; Cheng-Wen Wu

Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.

Published in:

Design & Test of Computers, IEEE  (Volume:26 ,  Issue: 2 )

Date of Publication:

March-April 2009

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