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Computing and Minimizing Cache Vulnerability to Transient Errors

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1 Author(s)
Wei Zhang ; Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, Carbondale, IL

Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance.

Published in:

Design & Test of Computers, IEEE  (Volume:26 ,  Issue: 2 )