An incremental PGA architecture for STBC MIMO decoding

Space-time block codes (STBC) are desirable for use in multiple-input multiple-output (MIMO) communications systems because they can be decoded using only linear computations involving multiplication and addition. However, the number of simple operations and storage required may not be trivial for practical applications. This paper describes a method of implementing STBC MIMO decoding in programmable gate array (PGA) hardware using an incremental approach that reduces resource and storage requirements as compared to a direct implementation. A three antenna rate-frac12 STBC code is used as an example, but the techniques are readily applicable to other codes.