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Electrical properties of single‐crystal silicon layers formed from polycrystalline silicon by solid phase epitaxy

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3 Author(s)
Wang, K.L. ; Electrical Engineering Department, University of California at Los Angeles, California 90024Stanford Electronics Laboratories, Stanford, California 94305 ; Li, G.P. ; Sigmon, T.W.

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The electrical evaluation of metal‐oxide‐semiconductor (MOS) capacitors fabricated on thin films formed by low‐temperature epitaxial crystallization of amorphized polysilicon layers on single‐crystal Si substrates is presented. Shallow dopant and deep‐level defect distributions are obtained using fast C(V) and deep‐level transient spectroscopy, respectively. The dominant deep‐level defects are observed to be at Ec -0.074 eV, Ec -0.15 eV, and Ec -0.46 eV. Both the shallow dopant and deep‐level defect distributions exhibit peak concentrations near the original poly/single‐crystal interface. These defects and impurities are attributed to gettering by oxygen of contaminant impurities. It is concluded from the data that these films are of suitable quality for MOS device fabrication, and techniques are suggested to further decrease the observed defect concentrations.

Published in:

Applied Physics Letters  (Volume:39 ,  Issue: 9 )

Date of Publication:

Nov 1981

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