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A floating-point systolic cell for fit-error computations in vision processing

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2 Author(s)
Malowany, M.E. ; McGill Res. Centre for Intelligent Machines, Montreal, Que., Canada ; Malowany, A.S.

A floating-point systolic cell architecture for a VLSI circuit to perform fit-error computations is proposed. The cell is intended for participation in a dedicated hardware system which extracts mean and Gaussian curvature maps from range images. The principles of the cell architecture are given as well as an outline of the curvature extraction procedure and the larger hardware environment for curvature extraction of which the array of new cells forms a part. Results are presented from applying a software version of the curvature extraction algorithm with this fit-error computation to a real range image in a general-purpose Sun computing environment. Performance estimates for the curvature extraction using the new dedicated hardware are compared to measured execution times in the general-purpose computing environment.<>

Published in:

Communications, Computers and Signal Processing, 1989. Conference Proceeding., IEEE Pacific Rim Conference on

Date of Conference:

1-2 June 1989