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Partitioning yield loss via test pattern structures and critical areas

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3 Author(s)
Evans, W.M. ; Nat. Semicond. Corp., South Portland, ME, USA ; Cyr, R. ; Wilson, D.

Yield loss detected at electrical test is attributable to various factors in the fabrication of semiconductor devices. The accurate partitioning of this yield loss to the appropriate tool or process segment is necessary for rapid yield improvements. In this paper we discuss a method of partitioning that uses production test patterns and associated critical areas. We discuss the calculation of critical area as used in this paper, as well as methods for determining relevant test pattern structures that relate to the product. This model relies on full loop test patterns designed to maximize the available information for micro yield modeling. This method has been used successfully in new product yield enhancement activities for bipolar products at NSFM. The partitioning starts with a division between systematic and random components as a result of wafer map analysis. We give an algorithm for determining the division of systematic and random components based on the wafermap (Sort) data. The random components are then broken down into various front-end (leakage) and backend (metal) issues. Although no validation has been made regarding the accuracy of the partition, the combined model has shown a greater than 90% correlation to reality over a high intensity ramp period of several months.

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1995. ASMC 95 Proceedings. IEEE/SEMI 1995

Date of Conference:

13-15 Nov 1995

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