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The goal of this paper is to examine the economic impact of improved overlay during the lithography process. The motivation for this work is the development at SPARTA of an interferometer able to compensate directly for air turbulence. This improved interferometer will allow better stage positioning, lens and reticle characterization, and alignment of wafers during exposure. In this paper, we examine the effects of improved overlay on integrated circuit (IC) yield and the resulting increase in value to the IC manufacturer for present and future IC generations.
Date of Conference: 13-15 Nov 1995