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Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

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4 Author(s)
Celebi, A. ; Dept. of Electron. & Telecommun. Eng., Univ. of Kocaeli, Kocaeli ; Urhan, O. ; Hamzaoglu, I. ; Erturk, S.

In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.

Published in:

Signal Processing Letters, IEEE  (Volume:16 ,  Issue: 6 )

Date of Publication:

June 2009

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