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Power-Aware Mapping of Probabilistic Applications onto Heterogeneous MPSoC Platforms

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3 Author(s)
Schranzhofer, A. ; Comput. Eng. & Networks Lab. (TIK), ETH Zurich, Zurich ; Jian-Jia Chen ; Thiele, L.

Multiprocessor SoC platforms have been adopted for a wide range of high performance applications. Task assignment and processing unit allocation are key steps in the design of predictable and efficient embedded systems. Provided that the probability distributions and mutual exclusion conditions for executing applications are known a priori, this paper explores the mapping of tasks onto processing units while minimizing the expected average power consumption. The underlying model considers static (leakage) and dynamic power. This study shows that deriving approximative solutions with a constant worst-case approximation factor in polynomial time is not achievable unless P=NP, even if a feasible task mapping is provided as an input. A polynomial-time heuristic algorithm is proposed that applies a multiple-step heuristic. Experimental results reveal the effectiveness of the proposed algorithm by comparing the derived solutions to the optimal ones, obtained via an integer linear program (ILP) specification.

Published in:

Real-Time and Embedded Technology and Applications Symposium, 2009. RTAS 2009. 15th IEEE

Date of Conference:

13-16 April 2009