By Topic

A 0.1–20 GHz Low-Power Self-Biased Resistive-Feedback LNA in 90 nm Digital CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Mingqi Chen ; Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL ; Jenshan Lin

In this letter, a 0.1-20 GHz low-power low noise amplifier (LNA) is presented. A novel self-biased resistive- feedback topology is proposed. Two inductors inside the feedback loop and a shunt-peaking inductor are exploited to extend the bandwidth. A PMOSFET with inductive degeneration is chosen as the load to boost the gain while maintaining low noise figure (NF) at high frequencies. A source-degeneration inductor is also introduced at the input transistor to ensure good input matching and stability over the entire bandwidth. All inductors are small due to the presence of feedback. The LNA was fabricated using a digital 90 nm CMOS process with 12.7 dB peak power gain, 3.3 dB minimum NF, and - 1 dBm peak input-referred third-order intercept point (IIP3). With 12.6 mW power consumption and 0.12 mm2 active area, this wideband LNA may replace distributed amplifiers (DAs) in many applications.

Published in:

Microwave and Wireless Components Letters, IEEE  (Volume:19 ,  Issue: 5 )