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A K -Band CMOS Distributed Doubler With Current-Reuse Technique

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3 Author(s)
Kun-You Lin ; Dept. of Electr. Eng. & Grad. Inst. of Commun. Eng., Nat. Taiwan Univ., Taipei ; Jhih-Yu Huang, ; Shih-Chieh Shin

A K-band distributed frequency doubler is developed in 0.18 mum CMOS technology. This doubler combines the distributed topology for broadband characteristics and current-reuse technique to improve the conversion gain. The high-pass drain line and high-pass inter-stage matching network are used to obtain a good fundamental rejection. A measured conversion gain of better than -12.3 -dB is obtained, and the fundamental rejection is better than 30 dB for the output frequency between 18 and 26 GHz. The dc power consumption is 10.5 mW with a chip size of 0.55 times 0.5 mm2.

Published in:

Microwave and Wireless Components Letters, IEEE  (Volume:19 ,  Issue: 5 )