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An equalisation-based digital background error-correction technique for successive approximation analogue-to-digital converters (SA-ADCs) is presented. This technique enables the size of the sampling capacitors to be scaled down to the kT/C limit without matching concerns. Therefore, for SA-ADCs with resolutions of 10 bits and above, the proposed low-cost, power-efficient digital calibration technique indicates a large power saving and scalability improvement in deeply scaled CMOS technology. Computer simulation validates the effectiveness of this technique for a SA-ADC with 12-bit resolution and 10% mismatch in its digital-to-analogue converter component. The effective number of bits is improved from 4.8 to 12.