Skip to Main Content
The basic operation of BJT-based floating-body 1T DRAM cells on SOI is analyzed with supportive numerical device simulation. Extreme sensitivity of the charging process (write ldquo1rdquo) to the offset (Deltat WB) between the word-line and bit-line voltage pulses is revealed and explained. The necessity of a positive Deltat WB for successful write ldquo1rdquo is related to establishing a high gate capacitance, which is the predominant charge-storage element in the BJT-based cell. Such charging underlies why a fully depleted (FD) cell, e.g., a FinFET, can work for BJT-based DRAM, without an independent bias for accumulation charge that is necessary in conventional FD-MOSFET DRAM cells for charge storage and data sensing. Furthermore, a bulk-accumulation effect in the BJT-based DRAM cell is revealed and described. It undermines the BJT operation and leads to ineffective charging and significant loss of sense margin when the cell body thickness is scaled.