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This paper presents a layout-based methodology to predict the exact physical location of a bridging defect inside a standard cell. It involves a number of techniques. First of all, most likely intracell bridging defects are identified through layout analysis and then converted into equivalent logic models. Next, we use a new defect-oriented formulation to generate test pattern for each candidate defect so as to further enhance the diagnostic resolution. Experimental results indicate that this methodology can remove 90% false defect candidates beyond gate-level diagnosis for four real designs and ISCAS'85 benchmark circuits.