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Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs

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5 Author(s)
Cordone, R. ; Dipt. di Tecnol. dell''Inf., Univ. degli Studi di Milano, Crema ; Redaelli, F. ; Redaelli, M.A. ; Santambrogio, M.D.
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This paper proposes a new model for the partitioning and scheduling of a specification on partially dynamically reconfigurable hardware. Although this problem can be solved optimally only by tackling its subproblems jointly, the exceeding complexity of such a task leads to a decomposition into two phases. The partitioning phase is based on a new graph-theoretic approach, which aims to obtain near optimality even if performed independently from the subsequent phase. For the scheduling phase, a new integer linear programming formulation and a heuristic approach are developed. Both take into account configuration prefetching and module reuse. The experimental results show that the proposed method compares favorably with existing solutions.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:28 ,  Issue: 5 )