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Self-Test Techniques for Crypto-Devices

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4 Author(s)
Di Natale, G. ; Lab. d''Inf. de Robot. et de Microelectron. de Montpellier, Montpellier, France ; Doulcier, M. ; Flottes, M.-L. ; Rouzeyre, B.

This paper describes a generic built-in self-test strategy for devices implementing symmetric encryption algorithms. Taking advantage of the inner iterative structures of crypto-cores, test facilities are easily set-up for circular self-test of the crypto-cores, built-in pseudorandom test generation and response analysis for other cores in the host device. Main advantages of the proposed test implementation are an architecture with no visible scan chain, 100% fault coverage on crypto-cores with negligible area overhead, availability of pseudorandom test sources, and very low aliasing response compaction for other cores.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 2 )