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A Fully Pipelined Architecture for the LOCO-I Compression Algorithm

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2 Author(s)
Merlino, P. ; Dept. of Electr., Manage. & Mech. Eng., Univ. of Udine, Udine ; Abramo, A.

This paper presents the design of a novel architectural implementation of the LOCO-I compression scheme, the lossless/near-lossless algorithm used inside the JPEG-LS standard. Differently from what previously reported in literature, the proposed design fully exploits the sequential nature of the algorithm by means of a pipelined architecture, without modifications to the original compression scheme. The result is a good performance circuit well fitted for field-programmable gate-array realization, thus devised for application in the wearable computers and remote sensing domains.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:17 ,  Issue: 7 )

Date of Publication:

July 2009

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