Acquisition time performance of a novel serial search acquisition scheme for chip-asynchronous DS/SS systems

We study the mean acquisition time performance of a novel serial search acquisition scheme for chip-asynchronous direct-sequence spread-spectrum systems. The sequences arising under the out-of-phase hypothesis are modeled as random sequences, and an appropriate likelihood ratio is used in a sequential probability ratio test (SPRT) to test for the true phase of the received sequence. A different (and commonly used) likelihood ratio is obtained for the SPRT if the out-of-phase sequences are modeled as zero sequences, and we use the performance under this model as a benchmark for comparison. An appropriate verification stage for the serial search scheme is designed based on fixed sample size (FSS) tests which employ the same likelihood ratio as used in the testing stage. A general expression for the mean acquisition time Er[T_acq] is derived, and the results indicate that the test statistic based on the random sequence model offers considerable savings in E[T_acq] for moderate to large values of chip SNR