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Study of trap generation in the Sc2O3/La2O3/SiOx gate dielectric stack by scanning tunneling microscopy

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6 Author(s)
Ang, D.S. ; School of Electrical and Electronic Engineering Block S2, Nanyang Technological University, Nanyang Avenue, Singapore 639798, Singapore ; Ong, Y.C. ; OShea, S.J. ; Pey, K.L.
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Through scanning tunneling microscopy, the rate of electrical stress induced trap generation in the vicinity of the tip/high-κ interface of the Sc2O3/La2O3/SiOx gate stack is observed to be much higher than that at the SiOx/Si interface, implying that the former is more susceptible to electrical stress induced wear out. This polarity dependence is discussed in the context of current trap generation models and is shown to be best explained by anode hot-hole effect induced by inherently lower surface plasmon threshold energy at the metal/high-κ interface and a higher hole trapping rate in the relatively thick high-κ.

Published in:

Applied Physics Letters  (Volume:93 ,  Issue: 24 )

Date of Publication:

Dec 2008

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