Unified retention model for localized charge trapping nonvolatile memory device

Retention after cycling in an NROM nonvolatile memory cell is investigated. Electrical characterizations combined with two-dimensional simulations were employed. By combining subthreshold current characterizations with gate-induced drain leakage measurements, the retention loss mechanisms are quantified and differentiated. A unified retention model for the NROM technology is proposed, incorporating both lateral charge transport in the nitride layer and hot carrier-induced interface-states formation. The fabrication conditions in the various studies reported in the literature and the resultant impact on interface-states formation are most likely the cause of the formally nonresolved debate regarding the origin of retention loss in NROM technology.