A sequential logic device realized by integration of in-plane gate transistors in InGaAs/InP

An integrated nanoelectronic circuit is fabricated from a high-mobility In_0.75Ga_0.25As/InP heterostructure. The manufactured device comprises two double in-plane gate transistors with a current channel of 1.1 μm in length and 100 nm in width. The two transistors are coupled to each other in a configuration that the source of one transistor is directly connected with one in-plane gate of the other transistor. Electrical measurements reveal that this device functions as an SR (set-reset) latch (a sequential logic device) with a gain of ∼4 in the logic swing at room temperature. The demonstrated device provides a simple circuit design for SR latches.