By Topic

Substrate engineering for high-performance surface-channel III-V metal-oxide-semiconductor field-effect transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yi Xuan ; School of Electrical and Computer Engineering and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907, USA ; Ye, P.D. ; Tian Shen

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.2822892 

High-performance inversion-type enhancement-mode n-channel In0.65Ga0.35As metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layer-deposited Al2O3 as gate dielectric are demonstrated. A 0.5 μm gate-length MOSFET with an Al2O3 gate oxide thickness of 10 nm shows a gate leakage current less than 5×10-6 A/cm2 at 4 V gate bias, a threshold voltage of 0.40 V, a maximum drain current of 670 mA/mm, and transconductance of 230 mS/mm at drain voltage of 2 V. More importantly, a model is proposed to ascribe this 80% improvement of device performance from In0.53Ga0.47As MOSFETs mainly to lowering the energy level difference between the charge neutrality level and conduction band minimum for In0.65Ga0.35As. The right substrate or channel engineering is the main reason for the high performance of the devices besides the high-quality oxide-semiconductor interface.

Published in:

Applied Physics Letters  (Volume:91 ,  Issue: 23 )