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Thermal annealing effects on the electrical characteristics of the back interface in nano-silicon-on-insulator channel

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2 Author(s)
Won-Ju Cho ; Department of Electronic Materials Engineering, Kwangwoon University, 447-1 Wolgye-dong, Nowon-gu, Seoul 139-701, Korea ; Ahn, Chang-Geun

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The electrical properties of the back interface between the thin silicon and buried-oxide layers of nano-silicon-on-insulator substrate were evaluated. The effects of rapid thermal annealing (RTA) process were investigated, and the distributions of interface states at the thin silicon/buried-oxide interface were estimated by using metal-point-contact field-effect-transistor method. The interface-states at the back interface were considerably increased by RTA process. The RTA higher than 800 °C contributes to the increase of acceptor-type interface states. The increased interface states were effectively reduced by conventional furnace annealing at 500 °C in nitrogen ambient.

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Applied Physics Letters  (Volume:90 ,  Issue: 14 )