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Vertical surround-gated silicon nanowire impact ionization field-effect transistors

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5 Author(s)
Bjork, M.T. ; IBM Research GmbH, Zurich Research Laboratory, Säumerstrasse 4, 8803 Rüschlikon, Switzerland ; Hayden, O. ; Schmid, H. ; Riel, H.
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One of the fundamental limits in the scaling of metal oxide semiconductor field-effect transistor technology is the room-temperature (RT) limit of ∼60 mV/decade in the inverse subthreshold slope. Here, the authors demonstrate vertical integration of a single surround-gated silicon nanowire field-effect transistor with an inverse subthreshold slope as low as 6 mV/decade at RT that spans four orders of magnitude in current. Operation of the device is based on avalanche breakdown in a partially gated vertical nanowire, epitaxially grown using the vapor-liquid-solid method. Low-power logic based on impact ionization field-effect transistors in combination with a vertical architecture is very promising for future high-performance ultrahigh-density circuits.

Published in:

Applied Physics Letters  (Volume:90 ,  Issue: 14 )

Date of Publication:

Apr 2007

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