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A 200 MHz CMOS phase-locked loop with dual phase detectors

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3 Author(s)
Ware, K.M. ; MIT, Cambridge, MA, USA ; Lee, H.-S. ; Sodini, C.G.

The authors describe a 200-MHz PLL (phase-locked loop) in a 2- mu m CMOS technology employing an untrimmed current-controlled ring oscillator (CCO). Two phase detectors are included: a phase-frequency detector (PFD) for fast acquisition during data preamble (100% pulse density), and a mixer phase detector to lock on actual data (in the presence of missing pulses). Simulation results and experimental data using an external current source suggest that using the bandgap reference, the CCO supply sensitivity will be 4%/V and the CCO temperature coefficient will be about 500 p.p.m./ degrees C. Internal input and output waveforms in lock were measured from buffered test pads with a low-capacitance wideband buffered probe.<>

Published in:

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Date of Conference:

15-17 Feb. 1989