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Probing nanoscale local lattice strains in advanced Si complementary metal-oxide-semiconductor devices

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10 Author(s)
Huang, J. ; Department of Electrical Engineering, University of Texas at Dallas, Richardson, Texas 75083 ; Kim, M.J. ; Chidambaram, P.R. ; Irwin, R.B.
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Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.2336085 

Local lattice strains in nanoscale Si complementary metal-oxide-semiconductor (MOS) transistors are directly measured by convergent beam electron diffraction (CBED). Through both high spatial resolution and high strain sensitivity of the CBED technique, compressive strains on the order of 10-3 from a p-type MOS transistor with a sub-100 nm gate length are detected. One-dimensional quantitative strain mapping is demonstrated. The tensile strains from a <100> channel n-type MOS transistor are observed at the <910> zone axis. It is found that the strain increases with the thickness of the silicon nitride-capping layer, which is consistent with the device’s electrical behavior.

Published in:

Applied Physics Letters  (Volume:89 ,  Issue: 6 )

Date of Publication:

Aug 2006

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