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A 3.3 V quad digital signaling interface transceiver

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10 Author(s)

This paper describes the low-power techniques used to design the Clock/Data recovery, Jitter Filter and the high current Line Driver circuits in a Quad Line Interface for DS1/CEPT applications.

Published in:

Low Power Electronics, 1995., IEEE Symposium on

Date of Conference:

9-11 Oct. 1995