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Spatial and energetic distribution of border traps in the dual-layer HfO2/SiO2 high-k gate stack by low-frequency capacitance-voltage measurement

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8 Author(s)
Wei-Hao Wu ; Department of Electronics Engineering, National Chiao Tung University, ED641, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan, Republic of China ; Tsui, Bing-Yue ; Chen, Mao-Chieh ; Hou, Yong-Tian
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Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high-k gate dielectrics, and these high-k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the HfO2/SiO2 high-k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high-k metal-oxide-semiconductor capacitors with n-type Si substrate.

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Applied Physics Letters  (Volume:89 ,  Issue: 16 )