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114 MFLOPS logarithmic number system arithmetic unit for DSP applications

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1 Author(s)
D. M. Lewis ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

An arithmetic core for DSP applications, comprising two multiplier/dividers and an adder/subtractor, using logarithmic number system (LNS) arithmetic, is described. For most operands, precision better than the worst-case precision of IEEE 754 is obtained. Three operations per cycle are performed using 69k transistors integrated in a 16 mm2 core in 1.2 μm CMOS, offering better performance than the best previous result in only 43% of the area. The use of a new interleaved memory ROM structure and a second-order function interpolator are the key techniques that result in reduced area. This modest area allows several core units to be integrated on a chip for high performance DSP applications

Published in:

IEEE Journal of Solid-State Circuits  (Volume:30 ,  Issue: 12 )