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Design considerations for 32-bit microprocessor TX3

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5 Author(s)

The architecture of the TX3 implementation of the TRON-CHIP32 specification is discussed. TX3 supports the full instruction set, including the decimal, floating-point, and other complex instructions. Average performance above 10-MIPS is expected. This performance level is obtained by the use of an 8-kB instruction cache, 8-kB data cache, decoded instruction loop buffer, three instruction execution units, and the ability to issue up to two instructions per cycle.<>

Published in:

Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers

Date of Conference:

Feb. 29 1998-March 3 1988

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