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A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology

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2 Author(s)
Crols, J. ; ESAT-MICAS, Katholieke Univ., Leuven, Belgium ; Steyaert, M.S.J.

An analog receiver front end chip realized in a 0.7 μm CMOS technology is presented. It uses a new, high performance, downconverter topology, called double quadrature downconverter, that achieves a phase accuracy of less than 0.3° in a large passband around 900 MHz, without requiring any external component or any tuning or trimming. A high performance low-IF receiver topology is developed with this double quadrature downconverter. The proposed low-IF receiver combines the advantages of both the classical IF receiver and the zero IF receiver: an excellent performance and a very high degree of integration. In this way, it becomes possible to realize a true fully integrated receiver front-end that does not require a single external component and which is, different from the zero-IF receiver, nonetheless totally insensitive to parasitic baseband signals and self-mixing products

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Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 12 )