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Suppression of DC bias stress-induced degradation of organic field-effect transistors using postannealing effects

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6 Author(s)
Sekitani, T. ; Quantum-Phase Electronics Center, School of Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan ; Iba, S. ; Kato, Y. ; Noguchi, Y.
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We fabricate pentacene field-effect transistors (FETs) showing a very small degradation in performance under a continuous DC bias stress. Pentacene FETs are manufactured on polyimide films with polyimide gate dielectric layers, and then encapsulated by poly-chloro-para-xylylene passivation layers, resulting in very flexible and heat-resistant devices. When such devices are annealed at 140 °C for 12 h in a nitrogen environment, the change in their source-drain current is 3±1% even after the application of continuous DC voltage biases of VDS=VGS=-40 V for 11 h. Furthermore, their mobility is increased by postannealing effects from 0.27 cm2/V sto 0.36 cm2/V s and their on/off ratio is also increased from 103 to 106.

Published in:
Applied Physics Letters  (Volume:87 ,  Issue: 7 )

Date of Publication: Aug 2005

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