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A novel GaAs power MESFET with low distortion characteristics employing semi-insulating setback layer under the gate

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5 Author(s)
Furukawa, H. ; Electron. Res. Lab., Matsushita Electron. Corp., Osaka, Japan ; Tateoka, K. ; Miyatsuji, Kazuo ; Sugimura, A.
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A low distortion GaAs power MESFET has been developed by employing a semi-insulating setback layer under the gate. The setback region was obtained by diffusing chromium from the Cr/Pt/Au gate metal in self-aligned manner. The novel power FET with the setback layer was found to be insensitive to surface trapping effects. They showed only 5-6 percent frequency dispersion of drain current at 1 MHz compared to DC condition. Because of this small frequency dispersion, the typical measurement FET, which has a surface setback layer, with a gate width of 36 mm exhibited 1.5 dB larger output power at 1 dB gain compression point than that of the FET without the setback layer. Moreover, in the π/4 shift-QPSK modulation that has been most popular in digital mobile communication system, the FET exhibited 11 dB smaller adjacent channel leakage power than the conventional one at the output power of 31.5 dBm

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Electron Devices, IEEE Transactions on  (Volume:43 ,  Issue: 2 )