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Design considerations for a bipolar implementation of SPARC

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4 Author(s)
Agrawal, A. ; Sun Microsyst. Inc., Mountain View, CA, USA ; Brown, E.W. ; Petolino, J. ; Peterson, J.R.

The design of Sun Microsystems' Scalable Processor Architecture (SPARC) using bipolar emitter-coupled-logic (ECL) process is considered. The BIT1 ECL process and design considerations for an ECL implementation of SPARC are described. Bus structures, cache concerns, interface considerations, and power density are discussed.<>

Published in:

Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers

Date of Conference:

Feb. 29 1998-March 3 1988