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Integration of IC Industry Feature Sizes with University Back-End-of-Line Post Processing: Example Using a Phase-Change Memory Test Chip

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8 Author(s)
Regner, J. ; Dept. of Electr. & Comput. Eng., Boise State Univ., Boise, ID ; Balasubramanian, M. ; Cook, B. ; Yingting Li
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We have demonstrated that back-end-of-line (BEOL) processing can successfully be performed in a university environment on die that have been fabricated at a foundry. This processing option enables universities to integrate state-of-the-art feature sizes with low resolution photolithography capabilities, such as achieved with a contact aligner, typically available at universities. With this capability, new device technologies and materials can be explored at the university level, where the basic research on the technology can occur without the timelines and expectations that are placed on product development in an industrial setting. By incorporating state-of-the-art feature sizes with these research efforts, the research results will be more applicable and more easily transferable to an industrial environment. In our project, we have demonstrated the integration of a foundry processed chip with the BEOL university processing through the fabrication of a small phase-change memory array with CMOS access transistors and addressing circuitry wherein the phase-change memory material was processed BEOL at Boise State University.

Published in:

Microelectronics and Electron Devices, 2009. WMED 2009. IEEE Workshop on

Date of Conference:

3-3 April 2009