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In this paper, we propose an efficacious memory array design method for low temperature poly-silicon technique. According to the four steps of our suggested method, we can draw a regular layout form of memory array. The regular property allows both ready calculation of the layout area and easy design of the memory controller. Since our proposed method does not leave any gaps in our layout, it is a powerful way to save area in the LTPS technique. It is also suitable for an electronic design automation (EDA) tool to implement a memory compiler with systematic and required size memory IP. Since the true single phase clock (TSPC) master-slave latch (MSL) is a fast and simple structure to implement a clocked storage element, we use TSPC-MSL as our memory cells to increase working frequency by a wide margin. Furthermore, according to our oblique memory array design method, we propose a verification formula to double-check whether our design is optimal or not at any time.