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A tessellator based on a vertex shader for bandwidth-efficient mobile 3D graphics

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4 Author(s)
Kyusik Chung ; Dept. of EECS, KAIST, Daejeon ; Chang-Hyo Yu ; Donghyun Kim ; Lee-Sup Kim

A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is proposed for a mobile 3D graphics engine. On-chip vertex generation of tessellation is implemented with 6.2% additional logic gate to a conventional vertex shader. An optimized vector dot product unit, a slim special function unit, and a unified data fetch unit reduce 25.6% of area. Dual-core of TES is fabricated using 0.18 um CMOS technology and processes 120 Mvertices/s at 100 MHz while consuming 272 mW of power.

Published in:

SoC Design Conference, 2008. ISOCC '08. International  (Volume:03 )

Date of Conference:

24-25 Nov. 2008