A tessellator based on a vertex shader for bandwidth-efficient mobile 3D graphics

A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is proposed for a mobile 3D graphics engine. On-chip vertex generation of tessellation is implemented with 6.2% additional logic gate to a conventional vertex shader. An optimized vector dot product unit, a slim special function unit, and a unified data fetch unit reduce 25.6% of area. Dual-core of TES is fabricated using 0.18um CMOS technology and processes 120Mvertices/s at 100MHz while consuming 272mW of power.