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SoC platform design with multi-channel bus architecture

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5 Author(s)
Younjin Jung ; Graduate School of Information and Communication, Hanbat National University, Daejeon, Korea ; Ok Kim ; Byoungyup Lee ; Hongkyun Jung
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We have designed an SoC platform with a multi-channel bus architecture which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of OpenRISC 1200 processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows more than one master to use the bus because of multiple channels. The proposed platform is implemented on Altera's EP2C70F672 FPGA device. As a result of the test program, the proposed platform has better efficiency by 26.58% than the SoC platform with shared bus on-chip bus.

Published in:

SoC Design Conference, 2008. ISOCC '08. International  (Volume:03 )

Date of Conference:

24-25 Nov. 2008