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Browse Conference Publications > SoC Design Conference, 2008. ... Help

High performance IPC hardware accelerator and communication network for MPSoCs

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2 Author(s)
Moonmo Koo ; Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul ; Soo-Ik Chae

In this paper, we explain a configurable IPC module for multimedia MPSoCs, which was implemented in a MPW chip that include three ARM7 CPU cores. According to the test results for an M-JPEG and a H.264 decoder, its IPC synchronization overheads are not more than 1% when the synchronization period is about 5000 cycles.

Published in:
SoC Design Conference, 2008. ISOCC '08. International  (Volume:03 )

Date of Conference: 24-25 Nov. 2008

Page(s):
III-21 - III-22
E-ISBN :
978-1-4244-2599-0
Print ISBN:
978-1-4244-2598-3
INSPEC Accession Number:
10574307
Conference Location :
Busan
Digital Object Identifier :
10.1109/SOCDC.2008.4815730
Product Type:
Conference Publications

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