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In this paper, we explain a configurable IPC module for multimedia MPSoCs, which was implemented in a MPW chip that include three ARM7 CPU cores. According to the test results for an M-JPEG and a H.264 decoder, its IPC synchronization overheads are not more than 1% when the synchronization period is about 5000 cycles.
SoC Design Conference, 2008. ISOCC '08. International (Volume:03 )
Date of Conference: 24-25 Nov. 2008