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Design of On-Chip Debug System for embedded processor

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5 Author(s)
Hyungbae Park ; Dept. of Electron. Eng., Pusan Nat. Univ., Busan ; Jingzhe Xu ; Jusung Park ; Jung-Hoon Ji
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In this paper, we introduce on-chip debug system (OCDS) which supports symbolic debugging at c-level using OCD integrated Debug-logic into target processor. The OCDS consist of SW debugger that supports a functionality of symbolic debugging, OCD (on-chip debugger) serving as a debugger of internal state of target processor, and Interface & Control block interfacing SW debugger and OCD. After OCD block is interfaced with 32 bit RISC processor core and then implemented with FPGA, OCD is connected by Interface & Control block, and SW debugger. The verification of the design is carried out through device recognition, carrying-out instructions of JTAG(joint test action group), reading and writing the internal registers of the processor and memory, and checking the emulation functions such as setting break-points and watch points.

Published in:

SoC Design Conference, 2008. ISOCC '08. International  (Volume:03 )

Date of Conference:

24-25 Nov. 2008