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Satisfying timing constraint is the most important issue in today's VLSI design. The recent increase of process variation, however, made it too difficult to predict the circuit timing accurately using traditional deterministic methods. Many statistical static timing analysis (SSTA) approaches have been proposed to deal with the impact of large process variation effectively. However, most of them focused on the gate-level design, and those for macro-level designs have not been well developed yet. This paper investigates the validity of applying SSTA to the macro-level designs by presenting preliminary experimental results that compare SSTA and the worst-case corner timing analysis in accuracy. In addition, this paper investigates how the process variation affects the usefulness of the macro-level SSTA.