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The use of Fair Y-Sim for optimizing mapping set selection in hardware/software co-design

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4 Author(s)
Adeluyi, O. ; Dept. of Comput. Eng., Chosun Univ., Gwangju ; Eun-ok Kim ; Jeong-A Lee ; Jeong-Gun Lee

This paper proposes a new hardware/software partitioning and mapping procedure based on a Y-chart design approach for the partitioning of stream based real-time video signal processing algorithms. The approach of this paper is to ensure ldquofairnessrdquo in the hardware-software partitioning by increasing the capacity of application functions to become candidates for mapping cases through the iterative equalization of the execution times by sub-partitioning the functions with excessively long execution times. Then, a simulation tool called Fair Y-Sim (fairy-sim) is developed to streamline the mapping set to the best cases based on some pre-specified metrics. Our experimental results show that when this is done in tandem with the Heuristic Algorithm for Reducing Mapping Sets (HARMS) we can obtain a mapping set streamlining ratio of up to 4.83% of the best mapping cases, while eliminating 95.17% of the initial mapping set based on their throughput values.

Published in:

SoC Design Conference, 2008. ISOCC '08. International  (Volume:02 )

Date of Conference:

24-25 Nov. 2008

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